In a semiconductor device, a test circuit for testing the function of the internal circuitry of that device is typically included. This test of the internal circuitry in a semiconductor device is to be executed before the shipping of the semiconductor device, and it is not intended to be conducted by a user of the semiconductor device. Consequently, various means are provided in the test circuit of the semiconductor device to prevent the inadvertent activation of the testing operation by the user.
A conventional testing method for a semiconductor device, such as a dynamic random access memory (DRAM), for example, involves the activation of a test circuit of the DRAM, that is, entry into a test mode, which is effected by the input of the address signal indicating the test mode in WCBR cycle. In this case, in order to prevent an erroneous entry into the test mode, the test mode is established such that it is entered only when a voltage higher than a specified power supply voltage is applied to an external terminal of the DRAM. Because a voltage higher than the power supply voltage is not applied to the external terminal of the DRAM during the normal use of the DRAM, the test mode is not entered erroneously during normal use.
The aforementioned WCBR means the operation in which the write enable signal WE and column address strobe signal CAS become low in level prior to the row-address strobe signal RAS.
In the conventional DRAM test, for each test, the address indicating the intended test mode is defined, and the intended test is executed when the address indicating a specified test is input. In other words, the test mode and the address codes indicating the applicable test mode have a 1 to 1 correspondence, and the test circuit corresponding to each test mode is individually provided inside the DRAM.
For the word line stress test, the address indicating its test is defined, and also, for the disturb test, the address indicating its test is defined. Thus, the test circuits for executing the word line stress test and the disturb test are provided individually.
FIG. 8 shows a conventional test mode entry circuit of a DRAM. A decoder circuit 81 provides a test mode signal as an output indicating the detection of an address signal indicative of a specified test as input thereto. The test mode signal is the signal indicating the entry of the test mode.
In this conventional test mode entry circuit, because the decoder output for the address indicating the test mode is used as is as the test mode signal, when a different address is input in the next WCBR cycle, only the test mode signal of the test mode entry circuit corresponding to that address becomes active, while the other test mode signals become nonactive. Therefore, it is impossible to enter a number of tests at the same time.
FIG. 9 shows the details of the circuits of the decoder circuit 81 of the test mode entry circuit shown in FIG. 8. The decoder circuit 81 comprises two NAND circuits, NAND 91, 92, a NOR circuit, NOR 91, and inverters, IN 91, 92. This circuit is set to output, during a WCBR cycle, a high level signal when the values of the lower 5 bits of the address signal are 0, 1, 1, 0, 0, that is, when they are 0Bh in hexadecimal notation. In FIG. 9, A2 and A3 are the logic signals of the respective bits to which the address signals correspond, and A4B, A1B, A0B are the inverted signals of respective bits to which the address signals correspond.
The entry into the test mode as conventionally employed involves the application of a voltage higher than the supply voltage to a specific terminal of the semiconductor device undergoing testing. Deterioration of a transistor of the semiconductor device that is caused by the application of such high voltage is a problem. Also, during burn-in testing, a type of semiconductor device test procedure, a voltage higher than the supply voltage is applied to each terminal of the semiconductor device. If the test mode for the internal circuitry is entered erroneously during burn-in testing, an incorrect testing operation results.
Furthermore, in the conventional test circuit, the test mode and the address code indicating the test mode are to correspond 1 to 1, and the test circuit corresponding to each test mode is provided individually inside the semiconductor device. Accordingly, with the increase in the number of types of test modes, the area of the semiconductor chip occupied by the test circuit increases to an undesirable degree.
In addition, in the conventional test mode entry circuit, it is impossible to enter a number of tests at the same time, and each test is executed individually. Therefore, the number of test modes increases, making it necessary to increase the area of the semiconductor chip occupied by the test circuit.
It is therefore an object of the present invention to provide a semiconductor device test circuit, in which the test mode is not entered during normal use, and also the test mode can be entered without applying a voltage higher than the power supply voltage to an external terminal of the semiconductor device undergoing testing.
It is another object of the present invention to provide a semiconductor device test circuit, in which the percentage of the area of the semiconductor device occupied by the test circuit is reduced through decreasing the number of address codes by which the tests are defined.
Still another object of the present invention is to provide a semiconductor device test circuit, which is capable of curbing an increase in the area of the semiconductor chip occupied by the test circuit, by accommodating an increasing number of types of tests.
Yet another object of the present invention is to provide a semiconductor device test circuit, wherein a number of test modes can be entered simultaneously.